Oferta pracy

Digital IC Design Engineer

Proservia O firmie

  • Gdańsk, pomorskie

  • Ważna jeszcze 14 dni
    do: 15 paź 2020
  • Umowa o pracę, Kontrakt B2B
  • Pełny etat
  • Ekspert
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ManpowerGroup Solutions jest częścią ManpowerGroup – światowego lidera innowacyjnych rozwiązań dla rynku pracy, który od 2001 roku wspiera klientów i kandydatów w Polsce. Firma projektuje i dostarcza rozwiązania pomagające organizacjom osiągać lepsze wyniki finansowe, a kandydatom szybki rozwój kariery zawodowej w międzynarodowych korporacjach.

Obecnie dla jednego z naszych Klientów poszukujemy Kandydatów na stanowisko:
Digital IC Design Engineer
Praca Stała
Miejsce pracy: Gdańsk
Nr ref.: PDE/INT/GDA

Opis stanowiska

We look for engineers who are capable of converting the logic design into physical pre-silicon designs. As a Physical Design Engineer you make manufacturing possible- chips can’t be developed without the physical pre-silicon design.

Wymagania

Physical Design Engineers are experts in the full digital IC design flow and specifically in floorplanning, the complete Place and Route flow, Signoff Static Timing Analysis, Timing closure activities and physical verification. The scope of work includes the physical implementation of blocks in advanced TSMC processes (7nm and below), specifically, the following aspects of the physical flow:

1. Topographical synthesis of physical partitions

2. Create clock constraints & perform block level clock tree synthesis

3. Ownership of block level timing closure activities

4. Floorplanning of the blocks

5. Complete place & route of the blocks

6. Physical verification of the blocks

7. Signoff STA of the blocks

8. Creation of all necessary design views for integration into toplevel

9. Contribute to top-level design closure and signoff

10. Perform and ensure clean signoff checks for timing, physical verification, multi-voltage, formal & IRDROP for all agreed blocks

11. Organize regular review of the tasks in progress or completed

12. Complete all documentation associated with the above tasks

13. Responsible for identifying any RTL/documentation/flow bugs and logging bug reports for tracking purposes

14. Responsible for closing bug reports in a timely manner

15. Responsible for ensuring that there are no bugs found that would necessitate a stepping in the project.

16. Responsible for identifying design bugs and closing them off comprehensively or by clearly handing over to an acceptable owner

17. Work closely with & support RTL, DFX and physical teams

18. PT & ICC2 environment maintenance and updates as necessary.

Oferta

As a Physical Design Engineer you will be part of a talented team of engineers that take designs from register-transfer level (RTL) to complete physical implementation, in a fast-paced and technically challenging environment.

Osoby zainteresowane prosimy o przesyłanie aplikacji klikając w przycisk aplikowania.
Osoby zainteresowane ogłoszeniem prosimy o przesłanie aplikacji.

Prosimy o załączenie do aplikacji następującej klauzuli: "Niniejszym wyrażam dobrowolnie zgodę na przetwarzanie danych osobowych zawartych w moim CV przez ManpowerGroup Sp. z o.o. oraz ManpowerGroup Solutions Sp. z o.o. z siedzibą w Warszawie przy ul. Nowogrodzkiej 68, do celów związanych z procesem rekrutacji zgodnie z Ustawą z dnia 29 sierpnia 1997 roku o Ochronie Danych Osobowych (tekst jednolity: Dz. U. 2014 r. poz. 1182). Wyrażam także zgodę na udostępnianie moich danych osobowych innym podmiotom z ManpowerGroup oraz potencjalnym pracodawcom do celów związanych z procesem rekrutacji. Przysługuje mi prawo dostępu do moich danych i ich poprawiania."

Agencja zatrudnienia – nr certyfikatu 412.
Digital IC Design EngineerNumer ref.: PDE/INT/GDA

We look for engineers who are capable of converting the logic design into physical pre-silicon designs. As a Physical Design Engineer you make manufacturing possible- chips can’t be developed without the physical pre-silicon design.

Physical Design Engineers are experts in the full digital IC design flow and specifically in floorplanning, the complete Place and Route flow, Signoff Static Timing Analysis, Timing closure activities and physical verification. The scope of work includes the physical implementation of blocks in advanced TSMC processes (7nm and below), specifically, the following aspects of the physical flow:

1. Topographical synthesis of physical partitions

2. Create clock constraints & perform block level clock tree synthesis

3. Ownership of block level timing closure activities

4. Floorplanning of the blocks

5. Complete place & route of the blocks

6. Physical verification of the blocks

7. Signoff STA of the blocks

8. Creation of all necessary design views for integration into toplevel

9. Contribute to top-level design closure and signoff

10. Perform and ensure clean signoff checks for timing, physical verification, multi-voltage, formal & IRDROP for all agreed blocks

11. Organize regular review of the tasks in progress or completed

12. Complete all documentation associated with the above tasks

13. Responsible for identifying any RTL/documentation/flow bugs and logging bug reports for tracking purposes

14. Responsible for closing bug reports in a timely manner

15. Responsible for ensuring that there are no bugs found that would necessitate a stepping in the project.

16. Responsible for identifying design bugs and closing them off comprehensively or by clearly handing over to an acceptable owner

17. Work closely with & support RTL, DFX and physical teams

18. PT & ICC2 environment maintenance and updates as necessary.

As a Physical Design Engineer you will be part of a talented team of engineers that take designs from register-transfer level (RTL) to complete physical implementation, in a fast-paced and technically challenging environment.

Osoby zainteresowane prosimy o przesyłanie aplikacji klikając w przycisk aplikowania.

Ogłoszenie archiwalne