- Prof. Michała Bobrzyńskiego 46, 30-348 Kraków, PolskaKraków, małopolskie
- Ogłoszenie wygasło miesiąc temu
- Praktykant / Stażysta
Working Student - FPGA Design Verification Engineer
As part of our team you will contribute to requirements analysis and decomposition, design and implement the verification scenarios using System Verilog of new FPGA functionalities for 5G telecommunication system following the complete end to end project life cycle.
You will develop extensive knowledge of 5G system physical layer, Nokia hardware platforms and the way our customers are deploying them. You will contribute to develop innovative solutions to address Nokia strategy in the 5G domain and beyond.
This is an offer for working students (students aged below 26).
We work with:
- System Verilog, UVM
- Git, IDM
- Testing frameworks
- Version control and code review systems
- Continuous integration systems
- Education: on-going studies of Telecommunication, Computer Science, Electronics or a similar subject
- Good knowledge of English (both spoken and written)
- FPGA programming - verification skills: System Verilog, UVM
- Experience in FPGA verification or integration
- Matlab/Octave or similar tool knowledge
- Understanding of technical documentation and technical writing skills
- Telecommunication knowledge is an advantage
- Embedded system background knowledge is an advantage
- Verilog/VHDL knowledge is an advantage
- Good mathematical skills is an advantage
- Low level/platform programming & debugging tools knowledge
- Good programming skills with script languages (e.g. Python, Perl, Tcl) is an advantage
Flexible working hours
Visit our career portal: www.nokiakrakow.pl
Please be informed that we reserve ourselves the right to contact only with selected candidates.